NVIDIA Fermi - GTX 470 GTX 480

[xbrian88]

Next Generation CUDA Architecture, Code Named Fermi

Fermi is Nvidia's new GPU architecture that's going to be the basis for all of its upcoming graphics cards. With 512 cores and 3 billion transistors, it will nuke Crysis.
The architecture really is a huge leap forward, according to people who've gone through it in-depth. Interestingly, the huge focus for Fermi is GPU computing. The first actual goods coming out using Fermi should be the GT300 series cards, which, besides the 512 cores sorted into 16 streaming processors with 32 cores each, uses a brand new GDDR5 memory setup.
PC Perspective has an epic write-up breaking down Fermi in detail that's worth a whirl, and of course Nvidia's got lots of fluff themselves all about Fermi. Strangely, they don't explain the name, which sounds like a sad little poodle.

Specifiche Fermi:

As the foundation for NVIDIA’s family of next generation GPUs namely GeForce®, Quadro® and Tesla® − “Fermi” features a host of new technologies that are “must-have” features for the computing space, including:

• C++, complementing existing support for C, Fortran, Java, Python, OpenCL and DirectCompute.
• ECC, a critical requirement for datacenters and supercomputing centers deploying GPUs on a large scale
• 512 CUDA Cores™ featuring the new IEEE 754-2008 floating-point standard, surpassing even the most advanced CPUs
• 8x the peak double precision arithmetic performance over NVIDIA’s last generation GPU. Double precision is critical for high-performance computing (HPC) applications such as linear algebra, numerical simulation, and quantum chemistry
• NVIDIA Parallel DataCache™ - the world’s first true cache hierarchy in a GPU that speeds up algorithms such as physics solvers, raytracing, and sparse matrix multiplication where data addresses are not known beforehand
• NVIDIA GigaThread™ Engine with support for concurrent kernel execution, where different kernels of the same application context can execute on the GPU at the same time (eg: PhysX® fluid and rigid body solvers)
• Nexus– the world’s first fully integrated heterogeneous computing application development environment within Microsoft Visual Studio
• "3.0B transistors @ TSMC, 40nm
• 2 x 16-way FMA SM, IEEE754-2008, 16 SMs
• Each SM has four SFUs
• 384-bit GDDR5
• ~650/1700/4200MHz (core/shader/memory)
• 16 pixels clock address and filter per SM
• 48 ROPs, 8Z/C clock
• 64KiB L1/smem per SM (48/16 or 16/48 per clock config, not user programmable as far as I know, at least not yet)
• Unified 768 KiB L2 (not partitioned now, so a write to L2 from any SM is visible to all others immediately)
• Unified memory space (hardware TLB, 1TiB address, 40-bit if my brain's working)
  
  
  

"The graph below is one of transistor count, not die size. Inevitably, on the same manufacturing process, a significantly higher transistor count translates into a larger die size. But for the purposes of this article, all I need to show you is a representation of transistor count.



See that big circle on the right? That's Fermi. NVIDIA's next-generation architecture.

NVIDIA astonished us with GT200 tipping the scales at 1.4 billion transistors. Fermi is more than twice that at 3 billion. And literally, that's what Fermi is - more than twice a GT200.

At the high level the specs are simple. Fermi has a 384-bit GDDR5 memory interface and 512 cores. That's more than twice the processing power of GT200 but, just like RV870 (Cypress), it's not twice the memory bandwidth.



The architecture goes much further than that, but NVIDIA believes that AMD has shown its cards (literally) and is very confident that Fermi will be faster. The questions are at what price and when.

The price is a valid concern. Fermi is a 40nm GPU just like RV870 but it has a 40% higher transistor count. Both are built at TSMC, so you can expect that Fermi will cost NVIDIA more to make than ATI's Radeon HD 5870.

Then timing is just as valid, because while Fermi currently exists on paper, it's not a product yet. Fermi is late. Clock speeds, configurations and price points have yet to be finalized. NVIDIA just recently got working chips back and it's going to be at least two months before I see the first samples. Widespread availability won't be until at least Q1 2010.

I asked two people at NVIDIA why Fermi is late; NVIDIA's VP of Product Marketing, Ujesh Desai and NVIDIA's VP of GPU Engineering, Jonah Alben. Ujesh responded: because designing GPUs this big is "****ing hard".

Jonah elaborated, as I will attempt to do here today.

Architecting Fermi: More Than 2x GT200

NVIDIA keeps referring to Fermi as a brand new architecture, while calling GT200 (and RV870) bigger versions of their predecessors with a few added features. Marginalizing the efforts required to build any multi-billion transistor chip is just silly, to an extent all of these GPUs have been significantly redesigned.

At a high level, Fermi doesn't look much different than a bigger GT200. NVIDIA is committed to its scalar architecture for the foreseeable future. In fact, its one op per clock per core philosophy comes from a basic desire to execute single threaded programs as quickly as possible. Remember, these are compute and graphics chips. NVIDIA sees no benefit in building a 16-wide or 5-wide core as the basis of its architectures, although we may see a bit more flexibility at the core level in the future.

Despite the similarities, large parts of the architecture have evolved. The redesign happened at low as the core level. NVIDIA used to call these SPs (Streaming Processors), now they call them CUDA Cores, I’m going to call them cores.



All of the processing done at the core level is now to IEEE spec. That’s IEEE-754 2008 for floating point math (same as RV870/5870) and full 32-bit for integers. In the past 32-bit integer multiplies had to be emulated, the hardware could only do 24-bit integer muls. That silliness is now gone. Fused Multiply Add is also included. The goal was to avoid doing any cheesy tricks to implement math. Everything should be industry standards compliant and give you the results that you’d expect.

Double precision floating point (FP64) performance is improved tremendously. Peak 64-bit FP execution rate is now 1/2 of 32-bit FP, it used to be 1/8 (AMD's is 1/5). Wow.

NVIDIA isn’t disclosing clock speeds yet, so we don’t know exactly what that rate is yet.

In G80 and GT200 NVIDIA grouped eight cores into what it called an SM. With Fermi, you get 32 cores per SM.



The high end single-GPU Fermi configuration will have 16 SMs. That’s fewer SMs than GT200, but more cores. 512 to be exact. Fermi has more than twice the core count of the GeForce GTX 285.

In addition to the cores, each SM has a Special Function Unit (SFU) used for transcendental math and interpolation. In GT200 this SFU had two pipelines, in Fermi it has four. While NVIDIA increased general math horsepower by 4x per SM, SFU resources only doubled.

The infamous missing MUL has been pulled out of the SFU, we shouldn’t have to quote peak single and dual-issue arithmetic rates any longer for NVIDIA GPUs.

NVIDIA organizes these SMs into TPCs, but the exact hierarchy isn’t being disclosed today. With the launch's Tesla focus we also don't know specific on ROPs, texture filtering or anything else related to 3D graphics. Boo.

A Different Sort of Launch

Fermi will support DirectX 11 and NVIDIA believes it'll be faster than the Radeon HD 5870 in 3D games. With 3 billion transistors, it had better be. But that's the extent of what NVIDIA is willing to talk about with regards to Fermi as a gaming GPU. Sorry folks, today's launch is targeted entirely at Tesla.

A Real Cache Hierarchy

Each SM in GT200 had 16KB of shared memory that could be used by all of the cores. This wasn’t a cache, but rather software managed memory. The application would have to knowingly move data in and out of it. The benefit here is predictability, you always know if something is in shared memory because you put it there. The downside is it doesn’t work so well if the application isn’t very predictable.

Branch heavy applications and many of the general purpose compute applications that NVIDIA is going after need a real cache. So with Fermi at 40nm, NVIDIA gave them a real cache.

Attached to each SM is 64KB of configurable memory. It can be partitioned as 16KB/48KB or 48KB/16KB; one partition is shared memory, the other partition is an L1 cache. The 16KB minimum partition means that applications written for GT200 that require 16KB of shared memory will still work just fine on Fermi. If your app prefers shared memory, it gets 3x the space in Fermi. If your application could really benefit from a cache, Fermi now delivers that as well. GT200 did have an L1 texture cache (one per TPC), but the cache was mostly useless when the GPU ran in compute mode.

The entire chip shares a 768KB L2 cache. The result is a reduced penalty for doing an atomic memory op, Fermi is 5 - 20x faster here than GT200."

http://anandtech.com/video/showdoc.aspx?i=3651

http://www.nvidia.com/object/fermi_architecture.html

[xbrian88]

At long last, initial photos of the GT300, NVIDIA’s revolutionary new video card has been unvieled for the world to see, and to photograph!


At the GTC conference being hosted today in San Jose, Hardware Canucks got the chance to cover the event in hopes we would see the long awaited video card rear it’s head, and show itself it did!


Thankfully this thing doesn’t appear to be a behmoth like the competition. It takes a practical approach and simple dual slot cooler, however this is said to be the Telse model and therefore intended for workstations and GPU computing tasks, rather than gaming. Obviously the final product for desktops will likely look much different. The card also features only a single DVI port, but again, likely for the reasons mentioned above.


The images below feature NVIDIA’s CEO Jen-Hsun Huang holding the card and imaged on a 3D screen (hence the blur).

NVIDIA Fermi Architecture Whitepaper.pdf

[xbrian88]

riservato 2

[xbrian88]

riservato 3

[xbrian88]

riservato 4

[xbrian88]

riservato 5

mod schede video,scateniamoci

[xbrian88]

[xbrian88]

GF100/Fermi: The Gaming Part(?)
(Some things a rumour. By Rys)
- And the slide unblurred -

"3.0B transistors @ TSMC, 40nm
2 x 16-way FMA SM, IEEE754-2008, 16 SMs
Each SM has four SFUs
384-bit GDDR5
~650/1700/4200MHz (core/shader/memory)
16 pixels clock address and filter per SM
48 ROPs, 8Z/C clock
64KiB L1/smem per SM (48/16 or 16/48 per clock config, not user programmable as far as I know, at least not yet)
Unified 768 KiB L2 (not partitioned now, so a write to L2 from any SM is visible to all others immediately)
Unified memory space (hardware TLB, 1TiB address, 40-bit if my brain's working)

Each SM dual-issues per clock on two half warps, for two clocks. Instructions can be mixed, so FP+INT, or FP+FP, or SFU+FP, etc. If DP instructions are running, nothing else runs. Although I don't think that's quite right, need to run some CUDA on a chip to test.

1.5K threads per SM in flight (1K in GT200), 32K FP32 registers per SM (up from 16K in GT200).

DP is half rate as mentioned, and it's a FMA too. All memories the chip talks to, from registers up, are ECC protected (potentially, nobody ships ECC GDDR5, and I think the chip will address 'PC' DDR3 for that in the end). Not sure what scheme or penalty.

New generation of PTX, CUDA 3.0. C++ in CUDA because of the unified address space.

Some new predication support, although it's really not clear how the hardware makes it happen. Seems you can predicate any instruction.

New atomic performance. Seems like it'll coalesce atomic ops in a warp and won't hit DRAM if the update fails, instead using L2 (GT200 replayed the transaction at DRAM hundreds of clocks later). The whitepaper explanation is wrong.

Seems RF per SM has enough ports (256) and support from the operand fetch hardware to sustain full FMA rate across the chip.

It can run multiple CUDA kernels now at the same time. Limit is 16 per chip (one per SM), but I think that'll be capped at 8.

I think the tesselator is a software pipe with very little hardware support, too."







http://forum.beyond3d.com/showpost.php?p=1...amp;postcount=1

[xbrian88]

nuove foto aggiunte

[SelfZeroing]

uhm...ripeto che se hanno un prezzo più basso delle 5870/50 passo ad nVidia. Una cosa...ma..manca l'HDMI?Oo